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ASIC Implementation of Linear Equalizer Using Adaptive FIR Filter

ASIC Implementation of Linear Equalizer Using Adaptive FIR Filter

Grande Naga Jyothi, Anusha Gorantla, Thirumalesu Kudithi
Copyright: © 2020 |Volume: 16 |Issue: 4 |Pages: 13
ISSN: 1548-3673|EISSN: 1548-3681|EISBN13: 9781799805182|DOI: 10.4018/IJeC.2020100105
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MLA

Grande Naga Jyothi, et al. "ASIC Implementation of Linear Equalizer Using Adaptive FIR Filter." IJEC vol.16, no.4 2020: pp.59-71. http://doi.org/10.4018/IJeC.2020100105

APA

Grande Naga Jyothi, Gorantla, A., & Kudithi, T. (2020). ASIC Implementation of Linear Equalizer Using Adaptive FIR Filter. International Journal of e-Collaboration (IJeC), 16(4), 59-71. http://doi.org/10.4018/IJeC.2020100105

Chicago

Grande Naga Jyothi, Anusha Gorantla, and Thirumalesu Kudithi. "ASIC Implementation of Linear Equalizer Using Adaptive FIR Filter," International Journal of e-Collaboration (IJeC) 16, no.4: 59-71. http://doi.org/10.4018/IJeC.2020100105

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Abstract

Power consumption plays a crucial role in the design of portable wireless communication devices, as it has a direct influence on the battery weight and volume required for operation. This article presents a novel design for a linear LMS equalizer for the optimization of filter order. The article describes the use of a variable length algorithm for dynamically updating the tap-length of the LMS adaptive filter to optimize the performance and for reducing the power in the adaptive filter core. An algorithm is applied to reduce and adjust the order of the filter in linear equalizer according to the channel conditions. The proposed design is implemented in the synopsis TSMC 65nm technology. The results from using the algorithm uses 28% less power when compared with the conventional 64-tap fixed length adaptive filter design. It has also been shown that the low-complexity of the additional circuitry needed for the variable length adaptive filter presents minimal overhead for this architecture.

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